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2SK2980
Silicon N Channel MOS FET High Speed Power Switching
REJ03G1061-0400 (Previous: ADE-208-571B) Rev.4.00 Sep 07, 2005
Features
* Low on-resistance RDS(on) = 0.2 typ. (VGS = 4 V, ID = 500 mA) * 2.5 V gate drive devices. * Small package (MPAK)
Outline
RENESAS Package code: PLSP0003ZB-A (Package name: MPAK)
D 3 1 2 G 1. Source 2. Gate 3. Drain
S
Note:
Marking is "ZZ-"
Rev.4.00 Sep 07, 2005 page 1 of 6
2SK2980
Absolute Maximum Ratings
(Ta = 25C)
Item Drain to source voltage Gate to source voltage Symbol VDSS VGSS Ratings 30 +12 -10 1.0 4 0.8 150 -55 to +150 Unit V V V A A W
Drain current ID Drain peak current ID(pulse)Note1 Channel dissipation Pch Note2 Channel temperature Tch Storage temperature Tstg Notes: 1. PW 10s, duty cycle 1 % 2. Value at when using alumina ceramic board (12.5 x 20 x 0.7 mm)
C C
Electrical Characteristics
(Ta = 25C)
Item Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Gate to source leak current Gate to source cutoff voltage Static drain to source on state resistance Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Note: 3. Pulse test Symbol V(BR)DSS V(BR)GSS IDSS IGSS VGS(off) RDS(on) RDS(on) |yfs| Ciss Coss Crss td(on) tr td(off) tf Min 30 +12 -10 -- -- 0.5 -- -- 1.2 -- -- -- -- -- -- -- Typ -- -- -- -- -- -- 0.2 0.3 2.0 155 75 35 12 30 35 30 Max -- -- -- 1.0 5.0 1.5 0.28 0.5 -- -- -- -- -- -- -- -- Unit V V V A A V S pF pF pF ns ns ns ns Test Conditions ID = 100 A, VGS = 0 IG = +100 A, VDS = 0 IG = -100 A, VDS = 0 VDS = 30 V, VGS = 0 VGS = 8 V, VDS = 0 ID = 10 A, VDS = 5 V ID = 500 mA, VGS = 4 V Note3 ID = 500 mA, VGS = 2.5 V Note3 ID = 500 mA, VDS = 10 V Note3 VDS = 10 V, VGS = 0, f = 1 MHz VGS = 4 V, ID = 500 mA, RL = 20
Rev.4.00 Sep 07, 2005 page 2 of 6
2SK2980
Main Characteristics
Power vs. Temperature Derating
1.6 100 Test condition : When using alumina ceramic board (12.5 x 20 x 0.7 mm) 1.2 30
Maximum Safe Operation Area
Channel Dissipation Pch (W)
Drain Current ID (A)
10 3
10 s 100 s
PW
0.8
0.4
0
50
100
150
200
m s = 10 (1 DC 0.3 sh ms Op ot ) Operation in er 0.1 at this area is ion limited by RDS(on) 0.03 Ta = 25C 0.01 3 0.1 0.3 1 10 30
1
1
100
Ambient Temperature Ta (C)
Drain to Source Voltage VDS (V)
Typical Output Characteristics
1.0 4V 2.5 V Pulse Test 2V 1.0
Typical Transfer Characteristics
Drain Current ID (A)
Drain Current ID (A)
0.8
0.8 75C
25C
0.6 1.8 V
0.6
Tc = -25C
0.4
0.4
0.2
VGS = 1.5 V
0.2
VDS = 10 V Pulse Test
0
2
4
6
8
10
0
1
2
3
4
5
Drain to Source Voltage VDS (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage
Drain to Source Saturation Voltage VDS (on) (V)
0.5 Pulse Test
Gate to Source Voltage VGS (V) Static Drain to Source on State Resistance vs. Drain Current
2 Pulse Test 1 0.5
VGS = 2.5 V
0.4
0.3
0.2
Static Drain to Source on State Resistance RDS (on) ()
ID = 1 A 0.5 A 0.2 A
0.2 0.1 0.05 0.1
4V
0.1
0
2
4
6
8
10
0.2
0.5
1
2
5
Gate to Source Voltage VGS (V)
Drain Current ID (A)
Rev.4.00 Sep 07, 2005 page 3 of 6
2SK2980
Static Drain to Source on State Resistance vs. Temperature
0.5 ID = 0.1 A, 0.2 A, 0.5 A 0.4
VGS = 2.5 V
Static Drain to Source on State Resistance RDS(on) ()
Forward Transfer Admittance vs. Drain Current
Forward Transfer Admittance |yfs| (S)
5 2 1 0.5 75C 0.2 0.1 0.05 0.01 0.02
VDS = 10 V Pulse Test
Tc = -25C 25C
0.3
0.2 4V 0.1 0 -40
0.1 A, 0.2 A, 0.5 A
Pulse Test 0 40 80 120 160
0.05 0.1
0.2
0.5
1
Case Temperature
Tc
(C)
Drain Current ID (A)
Typical Capacitance vs. Drain to Source Voltage
Drain to Source Voltage VDS (V)
1000 500
VGS = 0 f = 1 MHz
Dynamic Input Characteristics
ID = 1 A
Capacitance C (pF)
40
16
100 50 20 10 5 0 10 20 30 40 50 Ciss Crss
30
VDS VGS
V DD = 5 V 10 V 20 V
12
20
8
10
VDD = 20 V 10 V 5V
4 0 10
0
2
4
6
8
Drain to Source Voltage VDS
(V)
Gate Charge
Qg (nc)
Switching Characteristics
Reverse Drain Current IDR (A)
200 1.0
Reverse Drain Current vs. Source to Drain Voltage
Switching Time t (ns)
100 50 20 10 5 2 1 0.1 0.2
VGS = 4 V, VDD = 10 V PW = 2 s, duty < 1 % td(off) tf td(on) tr
0.8
0.6
5V
VGS = 0
0.4
0.2 Pulse Test 0 0.4 0.8 1.2 1.6 2.0
0.5
1
2
5
10
Drain Current
ID (A)
Source to Drain Voltage
VSD (V)
Rev.4.00 Sep 07, 2005 page 4 of 6
Gate to Source Voltage
200
Coss
VGS (V)
50
20
2SK2980
Switching Time Test Circuit
Vin Monitor D.U.T. RL VDD = 10 V Vout Monitor Vin Vout Vin 4V 50 10% 10% 10%
Waveform
90%
90% td(on)
90% td(off) tf
tr
Rev.4.00 Sep 07, 2005 page 5 of 6
2SK2980
Package Dimensions
JEITA Package Code SC-59A RENESAS Code PLSP0003ZB-A Package Name MPAK(T) / MPAK(T)V, MPAK / MPAKV MASS[Typ.] 0.011g
D e
A
Q
c
E
HE
L A A xM S A b
L1 A3 e
LP
Reference Symbol Dimension in Millimeters
A2
A
A1 S b b1 c b2 A-A Section
e1
c1
I1
Pattern of terminal position areas
A A1 A2 A3 b b1 c c1 D E e HE L L1 LP x b2 e1 I1 Q
Min 1.0 0 1.0 0.35 0.1 2.7 1.35 2.2 0.35 0.15 0.25
Nom
1.1 0.25 0.42 0.4 0.13 0.11 1.5 0.95 2.8
Max 1.3 0.1 1.2 0.5 0.15 3.1 1.65 3.0 0.75 0.55 0.65 0.05 0.55 1.05
1.95 0.3
Ordering Information
Part Name 2SK2980ZZ-TL-E 2SK2980ZZ-TR-E Quantity 3000 pcs 3000 pcs Taping Taping Shipping Container
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product.
Rev.4.00 Sep 07, 2005 page 6 of 6
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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